-------------------------------------------------------------------------------
-- 
-- 
-- 
-- 
-------------------------------------------------------------------------------


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.mydesignpkg.ALL;

ENTITY testdesign IS
  -- empty entity for test benches	
END testdesign;

ARCHITECTURE mytest OF testdesign IS
	SIGNAL w1, w2 : STD_LOGIC;                   --  input signals
	SIGNAL wvec : STD_LOGIC_VECTOR(3 DOWNTO 0);  --  output signals
TYPE test_vector IS RECORD
    w1 : STD_LOGIC;
    w2 : STD_LOGIC;
    wvec : STD_LOGIC_VECTOR(3 DOWNTO 0);
END RECORD;
TYPE test_vector_array IS ARRAY (natural RANGE<>) OF test_vector;
CONSTANT test_vectors : test_vector_array := (
    ( w1 => '0', w2 => '0', wvec => "0010"),
    ( w1 => '0', w2 => '1', wvec => "0101"),
    ( w1 => '1', w2 => '0', wvec => "1101"),
    ( w1 => '1', w2 => '1', wvec => "1010")
);

BEGIN
	--  instantiate unit under test
  uut: unitname PORT MAP (w1=>w1, w2=>w2, wvec=>wvec);
    --  apply test vectors and check results
  verify: PROCESS
        VARIABLE vector : test_vector;
        VARIABLE errors : BOOLEAN := false;
        BEGIN

          FOR i IN test_vectors'RANGE LOOP
              vector := test_vectors(i);  -- get vector i
              w1 <= vector.w1;
              w2 <= vector.w2;     -- schedule vector i
              WAIT FOR 20 ns;      -- wait for circuit to settle
              IF wvec /= vector.wvec THEN
                  ASSERT false         -- assert reports on false
                      REPORT "wvec value is wrong";
                      errors := true;
              END IF;

          END LOOP;

          ASSERT NOT errors
              REPORT "Test vectors failed."
              SEVERITY WARNING;
          ASSERT errors
              REPORT "Test vectors passed!"
              SEVERITY NOTE;
          WAIT;	
    END PROCESS;
END;

